//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Wed Nov 13 12:31:02 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target dec_digits_split_4bit.bd
//Design      : dec_digits_split_4bit
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "dec_digits_split_4bit,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=dec_digits_split_4bit,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=5,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "dec_digits_split_4bit.hwdef" *) 
module dec_digits_split_4bit
   (A0,
    A1,
    A2,
    A3,
    TNS,
    UTS);
  input A0;
  input A1;
  input A2;
  input A3;
  output [3:0]TNS;
  output [3:0]UTS;

  wire A0_1;
  wire A1_1;
  wire A2_1;
  wire A3_1;
  wire Add_1bit_0_CO;
  wire Add_1bit_0_Y;
  wire Add_1bit_1_CO;
  wire Add_1bit_1_Y;
  wire Add_1bit_2_CO;
  wire Add_1bit_2_Y;
  wire Add_1bit_3_CO;
  wire Add_1bit_3_Y;
  wire Add_1bit_4_CO;
  wire Add_1bit_4_Y;
  wire [3:0]xlconcat_0_dout;
  wire [3:0]xlconcat_1_dout;
  wire [0:0]xlconstant_0_dout;
  wire [0:0]xlconstant_1_dout;
  wire xup_2_to_1_mux_0_y;
  wire xup_2_to_1_mux_1_y;
  wire xup_2_to_1_mux_2_y;
  wire xup_2_to_1_mux_3_y;

  assign A0_1 = A0;
  assign A1_1 = A1;
  assign A2_1 = A2;
  assign A3_1 = A3;
  assign TNS[3:0] = xlconcat_1_dout;
  assign UTS[3:0] = xlconcat_0_dout;
  dec_digits_split_4bit_Add_1bit_0_0 Add_1bit_0
       (.A(A0_1),
        .B(xlconstant_1_dout),
        .CI(xlconstant_1_dout),
        .CO(Add_1bit_0_CO),
        .Y(Add_1bit_0_Y));
  dec_digits_split_4bit_Add_1bit_0_1 Add_1bit_1
       (.A(A1_1),
        .B(xlconstant_0_dout),
        .CI(Add_1bit_0_CO),
        .CO(Add_1bit_1_CO),
        .Y(Add_1bit_1_Y));
  dec_digits_split_4bit_Add_1bit_1_0 Add_1bit_2
       (.A(A2_1),
        .B(xlconstant_0_dout),
        .CI(Add_1bit_1_CO),
        .CO(Add_1bit_2_CO),
        .Y(Add_1bit_2_Y));
  dec_digits_split_4bit_Add_1bit_2_0 Add_1bit_3
       (.A(A3_1),
        .B(xlconstant_1_dout),
        .CI(Add_1bit_2_CO),
        .CO(Add_1bit_3_CO),
        .Y(Add_1bit_3_Y));
  dec_digits_split_4bit_Add_1bit_3_0 Add_1bit_4
       (.A(xlconstant_1_dout),
        .B(xlconstant_0_dout),
        .CI(Add_1bit_3_CO),
        .CO(Add_1bit_4_CO),
        .Y(Add_1bit_4_Y));
  dec_digits_split_4bit_xlconcat_0_0 xlconcat_0
       (.In0(xup_2_to_1_mux_0_y),
        .In1(xup_2_to_1_mux_1_y),
        .In2(xup_2_to_1_mux_2_y),
        .In3(xup_2_to_1_mux_3_y),
        .dout(xlconcat_0_dout));
  dec_digits_split_4bit_xlconcat_0_2 xlconcat_1
       (.In0(Add_1bit_4_CO),
        .In1(xlconstant_1_dout),
        .In2(xlconstant_1_dout),
        .In3(xlconstant_1_dout),
        .dout(xlconcat_1_dout));
  dec_digits_split_4bit_xlconstant_0_0 xlconstant_0
       (.dout(xlconstant_0_dout));
  dec_digits_split_4bit_xlconstant_0_1 xlconstant_1
       (.dout(xlconstant_1_dout));
  dec_digits_split_4bit_xup_2_to_1_mux_0_0 xup_2_to_1_mux_0
       (.a(Add_1bit_0_Y),
        .b(A0_1),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_0_y));
  dec_digits_split_4bit_xup_2_to_1_mux_0_1 xup_2_to_1_mux_1
       (.a(Add_1bit_1_Y),
        .b(A1_1),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_1_y));
  dec_digits_split_4bit_xup_2_to_1_mux_1_0 xup_2_to_1_mux_2
       (.a(Add_1bit_2_Y),
        .b(A2_1),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_2_y));
  dec_digits_split_4bit_xup_2_to_1_mux_2_0 xup_2_to_1_mux_3
       (.a(Add_1bit_3_Y),
        .b(A3_1),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_3_y));
endmodule
